1. Field of the Invention
The present invention relates to a successive approximation type of analog-to-digital (A/D) converter, and more particularly to, for example, a successive approximation type of analog-to-digital converter formed in a MOS (Metal-Oxide-Semiconductor) type of semiconductor integrated circuit, and a comparator for use therein.
2. Description of the Background
Analog-to-digital conversion circuits for converting analog signals into corresponding digital signals, or A/D converters, are classified into an integration system and a comparison system. As the comparison system, there have been known kinds of conversion system, such as a parallel comparison type and a successive approximation type. The successive approximation type of analog-to-digital conversion circuit is adapted, for example, for comparing an input analog voltage to be converted with a plurality of reference voltages in sequence from the MSB (Most Significant Bit) position toward the LSB (Least Significant Bit) position to thereby determine each bit value.
The successive approximation type of analog-to-digital conversion circuit is composed, for example, of a comparator for comparing an input voltage with comparison voltages, a comparison register for generating and determining a resultant voltage value from the comparison made by the comparator, and a digital-to-analog (D/A) conversion circuit for converting the resultant voltage value into a corresponding analog value.
Such a comparator for performing voltage comparison is disclosed, for example, by Japanese patent laid-open publication No. 195655/1996, in which a chopper type voltage comparator is protected from an error caused by noise.
In a successive approximation type of analog-to-digital converter, switches are provided in its digital-to-analog conversion circuit and voltage comparator such as to be turned on and off to compare the voltage of each bit. The switches are implemented by analog switches formed into CMOS (Complementary MOS) semiconductor circuits including NMOS, PMOS, N type and P type semiconductor devices. The analog switches are adapted to be turned on and off in response to voltage fed to the gate electrode of the transistors thereof. When the gate voltage varies, the parasitic capacitance of the transistors varies accordingly to cause switching noise to be generated. This switching noise worsens the accuracy of the digital-to-analog and analog-to-digital converters, as was a problem.
Further, in the voltage comparator, when an analog input voltage is sampled and held, corresponding electric charges are stored in its internal capacitors. In order to increase the rate of the sampling and holding, MOS transistors of a larger size have to be prepared for the analog switches. However, when the size of the MOS transistor is increased, switching noise becomes larger in proportion to its size to worsen the accuracy in analog-to-digital conversion, which has also been a problem.
Moreover, in order to heighten the accuracy in sequential analog-to-digital conversions, it is necessary to increase the specific accuracy of the capacitors for holding an analog input voltage. In that case, there is a limit in downsizing of the capacitors. Also, when the analog-to-digital converter is designed to store electric charges of a minute voltage level establishing its higher accuracy in resolution with its appropriate operating speed maintained, there has been a limit in the size reduction of the MOS transistors implementing the switches.